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typical application diagram pfc ballast control ic features ? pfc, ballast control and half bridge driver in one ic ? critical conduction mode boost type pfc ? no pfc current sense resistor required ? programmable preheat time & frequency ? programmable ignition ramp ? programmable over-current ? internal fault counter ? end-of-life protection ? lamp filament sensing & protection www.irf.com 1 ? capacitive mode protection ? brown-out protection ? dynamic restart ? automatic restart for lamp exchange ? thermal overload protection ? programmable deadtime ? internal 15.6v zener clamp diode on vcc ? micropower startup (150 a) ? latch immunity and esd protection packages 20-lead soic (wide body) 20-lead pdip ir2167(s) & pbf description the ir2167 is a fully integrated, fully protected 600v ballast control ic designed to drive all types of fluorescent lamps. pfc circuitry provides for high pf, low thd and dc bus regulation. externally programmable features such as preheat time & fre- quency, ignition ramp characteristics, and running mode operat ing frequency provide a high degree of flexibility for the ballast design engineer. comprehensive protection features such as protection from failure of a lamp to strike, filament f ailures, low ac line conditions, thermal overload, or lamp failure during normal operation, as w ell as an automatic restart function, have been included in the design. the heart of the ballast control section is a variable frequency oscillator with externally programmmable deadtime. precise control of a 50% duty cycle is accomplished using a t-flip-flop. r2 r3 l1 m1 r1 d1 c bus c ramp c ph c1 r4 rt c4 ct r run r ph r dt c vcc d bs c bs r supply r7 r cs m3 r9 r8 m2 d3 r10 c7 l2 d4 c5 c snubber r11 r5 r6 r oc c oc 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 ir2167 vdc cph rph rt run ct dt oc lo com vcc vb vs ho sd cs 11 12 10 9 comp zx pfc vbus c comp c2 r12 r13 d6 d5 d2 c3 c6 + rectified ac line - rectified ac line please note that this datasheet contains advance information that could change before the product is released to production. data sheet no. pd60184 rev f for new designs, we recommend ir?s product ir2166
ir2167(s) & pbf 2 www.irf.com symbol definition min. max. units v b high side floating supply voltage -0.3 625 v s high side floating supply offset voltage v b - 25 v b + 0.3 v ho high side floating output voltage v s - 0.3 v b + 0.3 v lo low side output voltage -0.3 v cc + 0.3 v pfc pfc gate driver output voltage -0.3 v cc + 0.3 i omax max. allowable output current (ho,lo,pfc) due to external power transistor miller effect -500 500 i rt r t pin current -5 5 v ct c t pin voltage -0.3 6.5 v dc vdc pin voltage -0.3 v cc + 0.3 i cph cph pin current -5 5 i rph rph pin current -5 5 i run run pin current -5 5 i dt deadtime pin current -5 5 v cs current sense pin voltage -0.3 6.5 v i cs current sense pin current -5 5 i oc over-current threshold pin current -5 5 i sd shutdown pin current -5 5 v bus dc bus sensing input voltage -0.3 v cc v i zx pfc inductor current, zero crossing detection input -5 5 i comp pfc error amplifier compensation current -5 5 i cc supply current (note 1) -20 20 dv/dt allowable offset suppl y voltage slew ratet -50 50 v/ns p d package power dissipation @ t a +25 c (20 lead pdip) ? 1.50 (20 lead soic) ? 1.25 rth ja thermal resistance, junction to ambient (20 l ead pdip) ? 85 (20 lead soic) ? 90 t j junction temperature -55 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com, all currents are defined positive into any lead. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. v c/w w c ma v ma ma ma
ir2167(s) & pbf www.irf.com 3 recommended operating conditions for proper operation the device should be used within the recommended conditions. all voltage parameters are absolute voltages referenced to com, all currents are defined positive into any lead symbol definition min. max. units v bs high side floating supply voltage v cc - 0.7 v clamp v s steady state high side floating supply offset voltage -3.0 600 v cc supply voltage v ccuv+ v clamp i cc supply current note 2 10 ma v dc v dc lead voltage 0 vcc v i sd shutdown lead current -1 1 i cs current sense lead current -1 1 c t c t lead capacitance 220 ? pf r dt deadtime resistance 1.0 ? k ? i rt r t lead current (note 3) -500 -50 i rph rph lead current (note 3) 0 450 i run run lead current (note 3) 0 450 i zx zero crossing detection lead current -1 1 ma t j junction temperature -40 125 o c v ua ma note 2: sufficient current should be supplied to the vcc pin to keep the internal 15.6v zener clamp diode on this pin regulating its voltage. note 3: due to the fact that the rt pin is a voltage-controlled current source, the total rt pin current is the sum of all of the parallel current sources connected to that pin. during the preheat mode, the total current flowing out of the rt pin consists of the rph pin current plus the current due to the rt resistor. during the run mode, the total rt pin current consists of the run pin current plus the current due to the rt resistor. electrical characteristics v cc = v bs = v bias = 14v +/- 0.25v, r t = 16.9k ? , c t = 470 pf, rph and run leads no connection, v cph = 0.0v, r dt = 6.1k ? , r oc = 20.0k ?, v cs = 0.5v, v sd = 2.0v, c l = 1000pf, t a = 25 o c unless otherwise specified. symbol definition min. typ. max. units test conditions v ccuv+ v cc supply undervoltage positive going 10.4 11.4 12.5 v cc rising from 0v threshold v uvhys v cc supply undervoltage lockout hysteresis 2.0 2.1 2.1 i qccuv uvlo mode quiescent current ? 250 400 v cc < v ccuv- i qccflt fault-mode quiescent current ? 100 350 sd = 5v, cs = 2v or tj > t sd i qcc quiescent v cc supply current 1.9 3.3 4.5 r t no connection, c t connected to com i cc50k v cc supply current, f = 48khz 4.0 5.0 6.0 v clamp v cc zener clamp voltage 14.0 15.6 16.5 v i cc = 10ma supply characteristics a ma v
ir2167(s) & pbf 4 www.irf.com electrical characteristics (cont.) v cc = v bs = v bias = 14v +/- 0.25v, r t = 16.9k ? , c t = 470 pf, rph and run leads no connection, v cph = 0.0v, r dt = 6.1k ? , r oc = 20.0k ?, v cs = 0.5v, v sd = 2.0v, c l = 1000pf, t a = 25 o c unless otherwise specified. floating supply characteristics symbol definition min. typ. max. units test conditions i qbs0 quiescent v bs supply current ? 0 10.0 v ho = v s i lk offset supply leakage current ? 0 50 v b = v s = 600v a pfc error amplifier characteristics symbol d efinition min. typ. max. units test conditions v bus vbus sense input threshold 3.7 4.0 4.3 v i vbus vbus sense input bias current ? ? 0.1 a gm error amplifier transconductance 40 90 130 mho run mode operation i source error amplifier output current sourcing 15 30 50 v bus = 3v i sink error amplifier output current sinking 5 30 50 v bus = 5v v oh(ea) error amplifier output voltage swing (hi state) 12.5 13.5 14.5 v bus = 3v v 0l(ea) error amplifier output voltage swing (lo state) ? 0.25 0.4 v bus = 5v a oscillator, ballast control, i/o characteristics symbol definition min. typ. max. units test conditions f osc oscillator frequency 41 44 47 r t = 16.9k ? , r dt = 6.1k ? , c t =470pf v ct+ upper c t ramp voltage threshold 3.6 4.0 4.4 v ct- lower c t ramp voltage threshold 1.8 2.0 2.2 v rt r t lead voltage 1.8 2.0 2.2 t dlo lo output deadtime 2.0 2.4 2.6 t dho ho output deadtime 2.0 2.4 2.6 khz sec v symbol definition min. typ. max. units test conditions i cph+ cph lead charging current 2.5 2.8 3.2 av cph = 0v i cph- cph lead discharge current 50 175 350 na v cph = 0v v cphign cph lead lgnition mode threshold voltage 3.6 4.1 4.4 v cphrun cph lead run mode threshold voltage 4.7 5.1 5.5 v cphclmp cph lead clamp voltage 6 10 11.5 i cph = 1 a preheat characteristics v symbol d efinition min. typ. max. units test conditions v 0v over voltage comparator threshold 4.0 4.3 4.5 v pfc over voltage comparator pfc zero current detector v zx zx lead comparator threshold voltage 1.7 2.0 2.3 v v zxhys zx lead comparator hysterisis 400 300 300 mv v zxclamp+ zx lead clamp voltage (high state) 6.0 7.5 9.0 v i zx = 1ma v
ir2167(s) & pbf www.irf.com 5 note 4: when the ic senses an overtemperature condition (tj > 160oc), the ic is latched off. in order to reset this fault latch, the sd lead must be cycled high and then low, or the v cc supply to the ic must be cycled below the falling undervoltage lockout threshold (v ccuv- ). electrical characteristics (cont.) v cc = v bs = v bias = 14v +/- 0.25v, r t = 16.9k ? , c t = 470 pf, rph and run leads no connection, v cph = 0.0v, r dt = 6.1k ? , r oc = 20.0k ?, v cs = 0.5v, v sd = 2.0v, c l = 1000pf, t a = 25 o c unless otherwise specified. rph characteristics symbol definition min. typ. max. units test conditions i rphlk open circuit rph lead leakage current ? 0.1 ? a v rph =5v,v rph =6v run characteristics symbol definition min. typ. max. units test conditions i runlk open circuit run lead leakage current ? 0.1 ? a v run = 5v protection circuitry characteristics symbol definition min. typ. max. units test conditions v sdth+ rising shutdown lead threshold voltage 4.8 5.25 5.4 v v sdhys shutdown lead threshold hysteresis 300 150 100 mv v sdeol+ rising shutdown lead end-of-life threshold 2.6 3.0 3.4 voltage v sdeol- falling shutdown lead end-of-life threshold 0.7 1.0 1.3 voltage v csth+ over-current sense threshold voltage 1.05 1.2 1.35 v csth- under-current sense threshold voltage 0.14 0.23 0.28 t cs over-current sense propogation delay 50 350 550 nsec delay from cs to lo #fault number of sequential over-current fault 4v < v cph <5.1v, cycles cycles before ic shuts down (ign mode) 25 50 75 cycles cycles @cs > 1.3v v vdc+ low v bus /rectified line input upper threshold 4.8 5.2 5.7 v vdc- low v bus /rectified line input lower threshold 2.7 3.1 3.5 t sd thermal shutdown junction temperature ? 160 ? o c note 4 v gate driver output characteristics symbol definition min. typ. max. units test conditions vol low level output voltage (pfc, lo or ho) ? 0 100 i o = 0 v oh high level output voltage (pfc, lo or ho) ? 0 100 v bias - v o, i o = 0 t r turn-on rise time (pfc, lo or ho) 50 85 200 t f turn-off fall time (pfc, lo or ho) 25 45 100 mv nsec v
ir2167(s) & pbf 6 www.irf.com lead assignments pin # symbol description 1 11 10 9 3 8 7 6 5 4 2 16 15 14 13 12 vdc com cs lo sd pfc vbus zx comp dt ct run rt rph cph dc bus sensing input preheat timing capacitor preheat frequency resistor & ignition capacitor oscillator timing resistor run frequency resistor oscillator timing capacitor deadtime programming shutdown input current sensing input low-side gate driver output ic power & signal ground logic & low-side gate driver supply high-side gate driver floating supply high voltage floating return high-side gate driver output pin assignments oc over-current (cs+) threshold programming 19 18 20 17 vb vs ho vcc pfc gate driver output bus voltage sense input zero-crossing, pfc inductor error amplifier compensation 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 ir2167 vdc cph rph rt run ct dt oc lo com vcc vb vs ho sd cs 9 10 12 11 zx comp vbus pfc
ir2167(s) & pbf www.irf.com 7 state diagram ignition ramp mode f ph ramps to f min cph charging @ i ph = 1 a rph = open circuit run = open circuit cs oc threshold enabled run mode f min ramps to f run cph charges to 10v clamp rph = open circuit run = 0v cs 0.2v threshold enabled sd 1.0v and 3.0v thresholds enabled vcc > 11.4v (uv+) and vdc > 5.1v (bus ok) and sd < 4.9v (lamp ok) and t j < 160c (t jmax ) cph > 5.1v (end of ignition ramp) vcc < 9.5v (vcc fault or power down) or vdc < 3.0v (dc bus/ac line fault or power down) or sd > 5.1v (lamp fault or lamp removal) power turned on fault mode fault latch set 1 / 2 -bridge off pfc off comp=0v i qcc ? 150 a cph = 0v vcc = 15.6v t j > 160c (over-temperature) cs > oc threshold for 55 cycles (failure to strike lamp or hard switching) or t j > 160c (over-temperature) cs > oc threshold (over-current or hard switching) or cs < 0.2v (no-load or below resonance) or t j > 160c (over-temperature) or sd < 1v or sd > 3v (end-of-life) sd > 5.1v (lamp removal) or vcc < 9.5v (power turned off) uvlo mode 1/2-bridge off pfc off comp=0v i qcc ? 150 a cph = 0v cph > 4.0v (end of preheat mode) preheat mode 1 / 2 -bridge @ f ph pfc enabled cph charging @ i ph = 3 a rph = 0v run = open circuit cs disabled all values are typical
ir2167(s) & pbf 8 www.irf.com functional block diagram over- temp detect level shift pulse filter & latch 2 4.0v 5.1v 3 5 9.5v 3.0v 5.1v 1 1.0ua 4 2.0v i rt 6 i ct = i rt 7 4.0v 2.0v cph rph rt run ct dt vdc q s r2 q r1 q t rq 20 18 19 vs ho vb 17 15 16 com lo vcc 15.6v 13 sd 14 0.2v cs q s rq qd r q clk q s r q under- voltage detect 2.0v 8 50ua 7.6v 7.6v 7.6v oc 10 9 11 12 pfc 4.3v vbus comp zx 7.6v 4.0v 1.0v q s r2 q r1 q s rq vcc 4.0v 3.0v q s rq q s r2 q r1 gm hi watch- dog timer fault counter
ir2167(s) & pbf www.irf.com 9 ballast control section timing diagrams normal operation cs ph ign run uvlo uvlo over-current threshold ct lo cs ho ct lo cs ho ct lo cs ho v cc uvlo+ 15.6v uvlo- v cph 4.0v 7.6v 5.1v ho lo v rph 2.0v v run 2.0v f start f preheat f min f run freq
ir2167(s) & pbf 10 www.irf.com ballast control section timing diagrams fault condition ct lo cs ho ct lo cs ho ct lo cs ho v cc uvlo+ 15.6v uvlo- v cph 4.0v 7.6v 5.1v v rph 2.0v v run 2.0v sd 5.2v ho lo sd > 5.1v cs ph ign run uvlo uvlo fault ph ign f start f ph f run f ign freq 2v
ir2167(s) & pbf www.irf.com 11 4 4.5 5 5.5 6 -25 0 25 50 75 100 125 temperature (c) sd(preheat, ignition) (v) sd+ threshold vs temperature (ir2167) (preheat, ignition) 0 0.5 1 1.5 2 2.5 3 3.5 4 -25 0 25 50 75 100 125 temperature (c) eol+, eol- (v) eol+, eol- threshold vs temperature (ir2167) (run mode) eol+ eol - 0.1 1 10 100 110100 rdt (k ? ) t dead ( s) 220pf 470pf 1nf 3.3nf 10nf t dea d vs rdt (ir2167) 0 25 50 75 100 125 150 175 200 -25 0 25 50 75 100 125 temperature (c) t rise lo, t fall lo (ns) t rise lo, t fa ll lo vs temperature (ir2167) t rise t fall
ir2167(s) & pbf 12 www.irf.com 5 7 9 11 13 15 -25 0 25 50 75 100 125 temperature (c) v ccuv +, v ccuv - (v) v ccuv +, v ccuv - vs temperature (ir2167) v ccuv + v ccuv - 0 2 4 6 8 -25 0 25 50 75 100 125 temperature (c) vcph ( ign , run ) (v) vcph ( ign , run ) vs temperature (ir2167) v run v ign 0 2 4 6 8 10 -25 0 25 50 75 100 125 temperature (c) vdc+, vdc- (v) vdc+, vdc- vs temperature (ir2167) vdc+ vdc- 3 3.5 4 4.5 5 -250255075100125 temperature (c) v bus +, v bus - (v) v bus threshold vs temperature (ir2167) vbus+ vbus-
ir2167(s) & pbf www.irf.com 13 0 5 10 15 20 25 30 -25 0 25 50 75 100 125 temperature (c) ilk ( a) ilk vs temperature (ir2167) 10000 100000 1000000 1000 10000 100000 r t ( ? ) frequency (hz) ct=220pf, rdt=5.6k ct=470pf, rdt=2.7k ct=1nf, rdt=1.2k frequency vs r t (ir2167) t dea d =1 sec 4 5 6 7 8 9 10 10000 100000 1000000 frequency (hz) i cc (ma) i cc vs frequency (ir2167) r dt =5.6k ? , ct=220pf 0 10 20 30 40 50 60 70 80 048121620 v bs (v) i qbs (ua) 75c 25c -25c i qbs vs v bs vs temperature (ir2167) 125c
ir2167(s) & pbf 14 www.irf.com 1000 10000 100000 1000000 1000 10000 100000 r t ( ? ) frequency (hz) c t=220pf, r dt=11k c t=470pf, r dt=6. 2k c t=1nf, rd t=3k c t=4. 7nf, rd t=1k c t=10nf, r dt=1k frequency vs r t (ir2167) 20 30 40 50 60 70 80 90 10000 100000 1000000 frequency (hz) tj (c) tj vs frequency (ir2167 dip) driving irf820's, vbus=400v ic driven b y s q uare wave
ir2167(s) & pbf www.irf.com 15 functional description under-voltage lock-out mode (uvlo) the under-voltage lock-out mode is defined as the state the ic is in when vcc is below the turn-on threshold of the ic. (to identify the different modes of the ic, refer to the state diagram shown on page 7 of this document). during under- voltage lock-out mode, the ho, lo and pfc driver outputs are low and the ct pin is connected to com through resis- tor r dt to disable the oscillator. also, the internal supply to the rt pin circuitry is shut off and pins cph, run, dt and comp are internally pulled to com. the ir2167 under- voltage lock-out mode is designed to maintain a very low supply current of less than 200 a, and to guarantee the ic is fully functional before the high side, low side and pfc drivers are activated. figure 1 shows an efficient supply using the start-up current of the ir2167 together with a charge pump from the ballast stage (r supply , c vcc , d cp1 and d cp2 ). figure 1: start-up and supply circuitry the v cc capacitor (c vcc ) is charged by current through supply resistor (r supply ) minus the start-up current drawn 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 ir2167 vdc cph rph rt run ct dt oc lo com vcc vb vs ho sd cs 11 12 10 9 comp zx pfc vbus + v bus + rectified ac line v bus return c bs d bs c vcc r cs r3 r4 c snubber r supply d cp2 d cp1 r2 c1 r1 half-bridge output by the ic. the value of (r supply ) is chosen to provide 2x the maximum start-up current to guarantee ballast start-up at low line input voltage. once the capacitor voltage on the vcc pin reaches the start-up threshold, the sd lead is be- low 5.1 volts and v vdc is greater than 5.1v, the ic turns on and lo and ho begin to oscillate. pfc does not begin to oscillate until the ic reaches preheat mode. preheat mode startup mode the ir2167 enters preheat mode when vcc exceeds the uvlo positive-going threshold. before preheat mode begins, the cph and rph pins are connected to com. (see figure 3). as preheat begins, the external capacitor c ph is charged up by an internal 3 a current source. c ph determines the preheat time which continues until the voltage on the cph pin charges to 4.0v. preheat mode is defined as the state the ic is in when the lamp filaments are being heated to their correct emission temperature. this is necessary for maximizing lamp life and reducing the required ignition voltage. at the onset of preheat mode, c vcc begins to discharge due to the increase in ic operating current (figure 2) above the available current through resistor r supply . however, the half-bridge output also begins to oscillate and the charge pump, consisting of c snubber , d cp1 and d cp2 , supply the current to charge capacitor c vcc and thus the voltage to the ic. the vcc voltage supplied to the ic is limited by the internal 15.6v zener clamp. c vcc and c snubber must be selected such that enough supply current discharge time internal vcc zener clamp voltage vhyst v uvlo+ v uvlo- charge pump output t v c1 r supply & c vcc time constant c vcc discharge figure 2: supply capacitor (cvcc) voltage
ir2167(s) & pbf 16 www.irf.com is available over all ballast operating conditions. bootstrap diode (d bs ) and supply capacitor (c bs ) comprise the supply voltage for the high-side driver circuitry. to guarantee that the high-side supply is charged up before the first pulse on ho, the first pulse from the output drivers comes from the lo pin. the preheat mode oscillation frequency of the half-bridge output is determined by the parallel combination of r ph and r t with the values of c t , r dt and an internal circuit as shown in figure 3. note that at the onset of preheat mode the initial startup frequency is much higher than the preheat frequency. the half-bridge output frequency then ramps down from this initial start-up frequency to the preheat mode frequency. this is to ensure that the instantaneous voltage across the lamp during the first few cycles of operation does not exceed the strike potential of the lamp. ignition mode when the cph pin charges up to 4.0v, ignition mode begins. at this time, the output of comp2 (figure 3) goes low, m1 2 4.0v 5.1v 3 5 9.5v 3.0ua 4 2.0v i rt 6 i ct = i rt 7 4.0v 2.0v cph rph rt run ct dt q s r2 q r1 quick restart logic c ramp c ph rt ct r run r ph r dt fault signal comp1 comp2 m1 m2 figure 3: oscillator section block diagram with external component connection turns off and cramp begins to charge. cramp determines the time it takes for the oscillator to ramp down from the preheat frequency to the ignition mode frequency. once the voltage on the rph lead reaches 2.0v, external resistor rph has no effect on the frequency that is now determined by external components rt, ct and rdt. this is the mini- mum frequency. by this time, the oscillator will have ramped down toward the resonance of the load circuit causing the lamp to ignite. run mode when the voltage on the cph pin reaches 5.1v, the ic en- ters run mode. at this time, the output of comp1 (figure 3) goes high which turns m2 on and pulls the run pin to com. the frequency is now controlled by external components r t , r run , c t and r dt . in certain cases it is necessary to have the run frequency higher than the ignition frequency to con- trol the power used by the load. figure 4 shows the ballast control sequence explained in the previous paragraphs.
ir2167(s) & pbf www.irf.com 17 f ph f run f min frequency t f start v cph 5v v rph 2v v run 2v preheat mode ignition ramp mode run mode figure 4: ir2167 ballast control sequence the control sequence used in the ir2167 allows the run mode operating frequency of the ballast to be higher than the ignition frequency (i.e., fstart > fph > frun > fign). this control sequence is recommended for lamp types where the ignition frequency is too close to the run frequency to ensure proper lamp striking for all production resonant lc compo- nent tolerances (please note that it is possible to use the ir2167 in systems where fstart > fph > fign > frun, simply by leaving the run pin open). the heart of this controller is an oscillator that resembles those found in many popular pwm voltage regulator ics. in its simplest form, this oscillator consists of a timing resistor and capacitor connected to ground. the voltage across the timing capacitor c t is a sawtooth, where the rising portion of the ramp is determined by the current in the rt lead, and the falling portion of the ramp is determined by an external deadtime resistor r dt . the oscillograph in figure 5 illustrates the relationship between the oscillator capacitor waveform and the gate driver outputs. this falling portion of the sawtooth waveform is referred to as deadtime, during which both ho and lo outputs are low. the deadtime can be programmed by means of the external r dt resistor. the rt input is a voltage-controlled current source, where the voltage is regulated to be approximately 2.0v. in order to maintain proper linearity between the rt pin current and the ct capacitor charging current, the value of the rt pin current should be kept between 50a and 500a. the rt pin can also be used as a feedback point for closed loop control. pfc section in most ac to dc power converters it is necessary to have the circuit act as a pure resistive load to the ac input line voltage. to achieve this, active power factor correction (pfc) can be implimented which, for an ac input line voltage, produces an ac input line current. it is also important to produce a sinusoidal input current which has a low total harmonic distortion (thd) and a high power factor (pf) (see figure 6). . figure 5: oscillator waveforms
ir2167(s) & pbf 18 www.irf.com figure 6: input voltage & current pf=0.96, thd=22% the approach used in the ir2167 is classified as running in critical conduction mode, in which the inductor current discharges to zero with each switching cycle. there is no need to sense the rectified ac line input voltage because it is already sinusoidal. therefore, the inductor current will naturally follow the sinusoidal voltage envelope as the pfc mosfet is turned on and off at a much higher frequency (>10khz) than the line input frequency (50 to 60hz). the circuit compares the dc bus voltage to a fixed reference voltage to determine the on-time of the pfc mosfet. the off-time is determined by the time it takes the l pfc current to drop to zero. this zero current level is detected by a secondary winding in l pfc that is connected to the zx pin. the result is a system where the switching frequency is free- running and constantly changing from a high frequency near the zero crossing of the ac input line voltage, to a lower frequency at the peaks. (see figures 7, 8 & 9). 0 0 0 i lpfc pfc pin zx pin near peak region of rectified ac line near zero crossing region of rectified ac line figure 7 : inductor current figure 8: boost inductor envelope & line voltage figure 9: boost fet on time vs line input
ir2167(s) & pbf www.irf.com 19 as the external capacitor on the comp pin begins to charge, the pfc mosfet on time duration increases. the gain of ota1 is at its maximum value (see figures 10 & 11). maximum gain is desireable to raise the bus voltage to its nominal value as quickly as possible. when the voltage at the vbus pin reaches 3v, the gain of ota1 decreases to its nominal value. the bus voltage continues to increase to its nominal value at which time the voltage measured at the vbus pin equals 4v. the gain of ota1 now increases to its maximum value and remains there until the run mode. this is necessary because if vbus overshoots its nominal value, the circuit can react quickly to correct the error. also, during ignition, there is a sudden increase in load current which can cause the bus voltage to sag. with maximum gain, ota1 can quickly restore the dc bus voltage to its nominal value. when the ac line voltage is applied to the ballast, v cc rises to 15v. the pfc section is not enabled until the begin- ning of the preheat mode of operation. by not enabling the pfc section until the beginning of the preheat mode, the dc bus voltage in the ballast is not yet boosted to its nomi- nal running value. this helps alleviate the initial flash of the lamp when the half-bridge driver section first begins to switch. when the pfc circuit is first enabled, (see figure 10), the voltage at the vbus and comp pins is low. the pfc figure 10: pfc section mosfet is turned on with minimum on time and l pfc is shorted to ground and begins charging. the pfc mosfet then turns off and l pfc begins to discharge into the dc bus capacitor. comp4 has a 4.3v threshold with hysteresis so that if the voltage at the vbus pin overshoots the 4.3v threshold, the pfc mosfet will not turn on again until the voltage at the vbus pin drops to approximately 4.0v. this effectively limits ths maximum bus voltage to approximately 8% greater than the regulated level. in some instances, the line voltage may be too high. this causes the ac rectified line current to directly charge the dc bus capacitor without being boosted. since the current never drops to zero, the zx pin never goes high and the pfc mosfet never turns on. the watch dog timer circuit provides a pulse to turn on the pfc mosfet if no pulse is detected at the zx pin for 500ms. this enables the pfc circuitry to regulate the dc bus voltage at its nominal value 10 9 11 q s rq q s rq 1.0v vbus comp zx 7.6v 4.0v gm hi ota1 3.0v comp1 comp2 rs1 rs2 4.3v 12 pfc q s r2 q r1 q s r2 q r1 comp3 comp4 comp5 rs3 rs4 vcc run mode signal from fault detection circuitry 4.0v m1 watch- dog timer m2 c1
ir2167(s) & pbf 20 www.irf.com drive signals resultant signals note 1 : i comp in these regions is the output saturation current of the ota error amplifier 4.0 0 v cph 2.0 6.0 5.1 5.0 0 gm (max) quick start mode power boost mode power up mode run mode 1000 200 0 i comp note 1 note 1 note 1 note 1 4.0 0 v comp 2.0 6.0 4.0 4.3 0 v vbus 3.0 figure 11: pfc timing sequence
ir2167(s) & pbf www.irf.com 21 pfc over-current protection (optional) in case of fast on/off interruptions of the mains input voltage or during normal lamp ignition, the dc bus voltage level can decrease below the instantaneous rectified line voltage. should this occur, the pfc inductor current and pfc mosfet current can increase to high levels causing the pfc inductor to saturate and/or the pfc mosfet to become damaged. during fast on/off interruptions of the input mains voltage, the dc bus can drop during the time when the mains voltage is interrupted (off). since vcc is still above uvlo-, the ic will continue to operate and will increase the comp pin voltage to increase the pfc mosfet on-time due to the dropping of the dc bus. when the mains voltage returns again quickly, (before vcc reaches uvlo-), the on-time of the pfc mosfet is too long for the given mains voltage level resulting in high pfc inductor and mosfet currents that can saturate the inductor and/or damage the pfc mosfet (figure 12). figure 12, high pfc inductor current during fast mains on/off (upper trace: dc bus, 100v/div; middle trace: ac line input voltage, 100v/div; lower trace: pfc inductor current 1a/div). during lamp ignition, the dc bus can drop below the rectified ac line voltage causing current to conduct directly from the output of the rectifier, through the pfc inductor and diode, to the dc bus capacitor. this results in a low-frequency offset of current in the pfc inductor. since the zero-crossing detection circuit only detects the high-frequency zero- crossing of the inductor current, the pfc mosfet will turn on again each cycle before the inductor current has reached zero. this causes the pfc to work in a continuous conduction mode and the sum of the low-frequency and high-frequency components of current can saturate the pfc inductor and/ or damage the pfc mosfet. to protect against these conditions, a current sense resistor (rs) can be inserted between the source on the pfc mosfet and ground, and a diode (d4) connected from the top of this current-sensing resistor to the vbus pin (figure 13). 13, external over-current protection circuit rectified ac line 15 14 13 12 11 98-0265 com vcc vb vs ho 1 2 3 rt cph vbus 4 5 7 rph comp ct 6 7 8 pfc zx 10 cs lo 9 sd/eol 16 rs d4 1n4148 1 ? high current ground device ground
ir2167(s) & pbf 22 www.irf.com should high currents occur, the voltage across the current- sensing resistor (rs) will exceed the 4.3v over-voltage protection threshold at the vbus pin and the pfc mosfet will turn off safely limiting the current. the watch-dog timer will then restart the pfc as normal (figure 14). the current sensing resistor value should be selected such that the over-current protection does not false trip during normal operation over the entire line voltage range and load range. a current-sensing resistor value, for example, of 1.0 w will set the over-current protection threshold to about 5 a peak. figure 14, pfc inductor current limited using over-current protection circuit (upper trace: dc bus, 100v/div; middle trace: ac line input voltage, 100v/div; lower trace: pfc inductor current 1a/ div). the effect that these line and load conditions have on the performance of the ballast depends on the saturation level of the pfc inductor, the selection of the pfc mosfet, the dc bus capacitor value, the maximum on-time limit set by dzcomp, and, how fast vcc decreases below uvlo- when the dc bus drops during ignition (the 3v reset on the vbus pin does not become active until run mode). for these reasons, the ballast designer should perform these mains interrupt and ignition tests carefully to determine the robustness of their final design and to decide if this additional over-current protection circuit is necessary.
ir2167(s) & pbf www.irf.com 23 sensing the ac line voltage the first of these protection pins senses the voltage on the ac line by means of an external resistor divider (r1, r2 and capacitor c1) and an internal comparator with hysterisis. when power is first supplied to the ic at system startup, three conditions are required before oscillation is initiated: 1.) the voltage on the vcc pin must exceed the rising undervoltage lockout threshold (11.5v), 2.) the voltage at the vdc pin must exceed 5.1v, and 3.) the voltage on the sd pin must be below approximately 4.85v. if a low ac line condition occurs during normal operation, or if power to the ballast is shut off, the ac line will collapse prior to the vcc of the chip (assuming thevcc is derived from a charge pump off of the output of the half-bridge). in this case, the voltage on the vdc pin will shut the oscillator off, thereby protecting the power transistors from potentially hazardous hard switch- ing. approximately 2v of hysterisis has been designed into the internal comparator sensing the vdc pin, in order to account for variations in the ac line voltage under varying load conditions. when the ac line recovers, the chip re- starts from the beginning of the control sequence, as shown in timing diagram (see figure 16). lamp protection & automatic restart circuitry operation from oscillator section +v bus from lower lamp cathode r cs r3 r4 r5 r2 c1 r1 q2 r oc c2 v cc over- temp detect 2 4.0v 5.1v 9.5v 3.0v 5.1v 1 1.0ua 7 cph dt vdc q t rq 13 sd 14 0.2v cs q s rq qd r q clk q s r q under- voltage detect 5.1v 8 50ua 7.6v 7.6v 7.6v oc 3v 1v fault counter quick restart logic c oc 2v 1meg c4 from upper lamp cathode r7 r6 c3 figure 15: lamp protection & automatic restart circuitry block diagram with external component connection
ir2167(s) & pbf 24 www.irf.com run mode low vdc ct 4 vdc 3 5 cph 8 lo 15 ho-vs 15 restart figure 16: vdc lead fault and auto restart lamp presence and end-of-life detection the second protection pin, sd, is used for both shutdown and end-of-life detection. the sd pin would normally be connected to an external circuit that senses the presence of the lamp(s) and the voltage appearing across the lamp(s). an example circuit for a single lamp is shown in figure 17. during all modes of operation if the sd pin exceeds 5.1v (approximately 150mv of hysterisis is included to increase noise immunity), signaling either a lamp fault or lamp re- moval, the oscillator is disabled, both gate driver outputs are pulled low, and the chip is put into the micropower mode. since a lamp fault would normally lead to a lamp exchange, when a new lamp is inserted in the fixture, the sd pin would be pulled back to near ground potential. under these condi- tions a reset signal would restart the chip from the begin- ning of the control sequence, as shown in the timing dia- gram in figure 18. thus, for a lamp removal and replace- ment, the ballast automatically restarts the lamp in the proper man ner. in the run mode there are two additional thresholds enabled on the sd pin: 1v and 3v. these thresholds form a window and during normal lamp running the voltage appearing at the sd pin is maintained within these two levels. as a lamp nears its end-of-life, its running voltage will increase and the signal applied to the sd pin detects this by exceeding the window threshold width. the oscillator is disabled, both gate driver outputs are pulled low, and the chip is put into the micropower mode. + v bus + rectified ac line v bus return c bs d boot r supply c vcc r cs l res c res r ghs r gls c block c snubber r4 r3 r5 c2 d1 d2 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 ir2167 vdc cph rph rt run ct dt oc lo com vcc vb vs ho sd cs 11 12 10 9 comp zx pfc vbus c4 c3 d3 r7 r6 figure 17: lamp presence detection circuit connection (shaded area)
ir2167(s) & pbf www.irf.com 25 run mode sd mode ct 4 cph 8 lo 15 ho-vs 15 restart sd 5 figure 18: sd lead fault and auto restart half-bridge current sensing and protection the third pin used for protection is the cs pin, which is nor- mally connected to a resistor in the source of the lower power mosfet, as shown in figure 19. the cs pin is used to sense fault conditions such as failure of a lamp to strike, over-current during normal operation, hard switching, no load, and operation below resonance. if any one of these conditions is sensed, the fault latch is set, the oscillator is disabled, the gate driver outputs go low, and the chip is put into the micropower mode. the cs lead performs its sens- ing functions on a cycle-by-cycle basis in order to maximize ballast reliability. for the over-current, failure-to-strike, and hard switching fault conditions, an externally programmable, positive-going cs+ threshold is enabled at the end of the preheat time. the level of this positive-going threshold is determined by the value of the resistor r oc . the value of the resistor r oc is determined by the following formula: or , 6 - 55e v r + cs oc = oc + cs r 6 - 55e = v ? figure 19: half-bridge current sensing circuit connection (shaded area) for the under-current and under-resonance conditions, there is a negative-going cs- threshold of 0.2v which is enabled at the onset of the run mode. the sensing of this cs- threshold is synchronized with the falling edge of the lo output. figures 20, 21 and 22 are oscillographs of fault conditions. figure 20 shows a failure of the lamp to strike, figure 21 shows a hard switching condition and figure 22 shows an under-current condition. rectified ac line 1 / 2 bridge output c vcc r supply d1 d2 q2 q1 c snubbe r v bus return +v bus d boot c boot r cs r3 r gls r ghs r oc 1 2 3 4 5 9 10 20 19 18 17 16 12 11 ir2167 vdc cph rph rt run comp zx pfc com vcc vb vs ho vbus 6 7 8 15 14 13 ct dt oc lo sd cs
ir2167(s) & pbf 26 www.irf.com figure 20: failure of lamp to strike upper trace cs 1v/div lower trace vs 200v/div figure 21: hard switching condition upper trace cs 2v/div lower trace vs 200v/div figure 22: operation below resonance upper trace cs 200 mv/div lower trace vs 200v/div figure 23: auto restart for lamp replacement upper trace sd/eol 5v/div middle trace cph 5v/div lower trace vs 200v/div cs vs cs vs cs vs sd vs cph
ir2167(s) & pbf www.irf.com 27 recovery from such a fault condition is accomplished by cycling either the sd pin or the vcc pin. (see figure 23). when a lamp is removed, the sd pin goes high, the fault latch is reset, and the chip is held off in an unlatched state. lamp replacement causes the sd pin to go low again, reinitiating the startup sequence. the fault latch can also be reset by the undervoltage lockout signal, if vcc falls below the lower undervoltage threshold. bootstrap supply considerations power is normally supplied to the high-side circuitry by means of a simple charge pump from vcc, as shown in figure 24. figure 24 : typical bootstrap supply connection with vcc charge pump from half-bridge output (shaded area) a high voltage, fast recovery diode d boot (the so-called bootstrap diode) is connected between vcc (anode) and vb (cathode), and a capacitor c boot (the so-called bootstrap capacitor) is connected between the vb and vs leads. during half-bridge switching, when mosfet q2 is on and q1 is off, the bootstrap capacitor c boot is charged from the vcc decoupling capacitor, through the bootstrap diode d boot , and through q2. alternately, when q2 is off and q1 is on, the bootstrap diode is reverse-biased, and the bootstrap capacitor (which ?floats? on the source of the upper power mosfet) serves as the power supply to the upper gate driver cmos circuitry. since the quiescent current in this cmos circuitry is very low (typically 45 a in the on- state), the majority of the drop in the vbs voltage when q1 is on occurs due to the transfer of charge from the bootstrap capacitor to the gate of the power mosfet. design equations note: the results from the following design equations can differ slightly from experimental measurements due to ic tolerances, component tolerances, and oscillator over- and under-shoot due to internal comparator response time. step 1: program maximum ignition v oltage maximum lamp voltage is required during ignition. this will vary depending on the type of lamp, but 1600v is typical for a t8 lamp. as the frequency decreases from the preheat frequency to the resonant frequency, the voltage across the lamp increases. during ignition, only r t along with c t and d t determine the frequency. r ph and r run are not connected to com at this time. the value of r t should be chosen so that the desired ignition voltage is reached. the rt pin current and timing capacitor charging current are both approximately: the value of this current should be kept between 50 a and 500 a. the value for c t is computed as follows: and the ignition mode frequency is: t rt ct r v i i 0 . 2 = = ? ? ? ? ? ? ? ? ? = td f r c ign t t 2 1 1 () td c r f t t ign + = 2 1 ? ? ? ? ? ? ? ? ? = td f c r ign t t 2 1 1 rectified ac line 1 / 2 bridge output c vcc r supply d1 d2 q2 q1 c snubber v bus return +v bus d boot c boot r cs r3 r gls r ghs 1 2 3 4 5 9 10 20 19 18 17 16 12 11 ir2167 vdc cph rph rt run comp zx pfc com vcc vb vs ho vbus 6 7 8 15 14 13 ct dt oc lo sd cs
ir2167(s) & pbf 28 www.irf.com deadtime is equal to: the following graphs, figures 25 and 26, illustrate the relationship between the effective resistance (i.e. the parallel combination of resistors which programs the ct capacitor charging current) and the operating frequency. figure 25: f osc vs effective r t (t dead =2.0 sec) t dt c r td ? ? = 69 . 0 0 50 100 150 0 5 10 15 20 25 30 35 40 rt ( k ? ) freq (khz) ct=220pf,rdt=11k ct=470pf,rdt=6.2k ct=1nf,rdt=3k 0 50 100 150 200 250 0 5 10 15 20 25 30 35 40 rt (k ? ) freq (khz) ct=220pf, rdt=5.6k ct=470pf, rdt=2.7k ct=1nf, rdt=1.2k figure 26: f osc vs effective r t (t dead =1.0 sec) figure 27 illustrates the relationship between deadtime vs r dt. figure 27: deadtime vs rdt 0.1 1 10 1 10 100 rdt (k ? ) tdead (usec) ct = 220 pf ct = 470 pf ct = 1 nf
ir2167(s) & pbf www.irf.com 29 step 2: program maximum ignition current the ignition current should be limited to the rating of the lamp resonant inductor and the half-bridge mosfets. the saturation current of the lamp resonant inductor should be much lower than the current rating of the mosfets. under worst case conditions, the lamp resonant inductor should not be allowed to saturate. this current is controlled by the cs pin and the oc pin. the oc lead has an internal 50 a current source. this current through external resistor r oc determines the threshold on the cs pin. if the current through external resistor r cs exceeds a predetermined value, the ic shuts off. step 3: program preheat frequency the preheat frequency is determined by the parallel combination of r ph and r t along with c t and r dt . the frequency should be chosen so that the voltage across the lamp is much lower than the ignition voltage but still provides adequate heating of the filaments. during preheat, the current through the filaments is constant. however, as the filaments heat up, their resistance increases. this results in an increase in the voltage measured across the filaments, which indicates the hot to cold ratio. 4:1 is an acceptable ratio for proper heating ? ? ? ? ? ? ? ? + ? + ? ? = td c r r r r f t ph t ph t ph 2 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = td f c r td f c r ph t t ph t ph 2 1 1 1 2 1 1 step 4: program preheat time the preheat time is determined by external capacitor c ph . the preheat time required for a 4:1 hot to cold ratio can be observed by measuring the voltage across the filaments. the preheat time is calculated as follows: the ir2167 is held in preheat until c ph is charged to 4.0v. step 5: program the ignition mode time the difference in time between the preheat mode and the run mode is the ignition mode. the rate at which the fre- quency changes from preheat to run is determined by exter- nal resistor r ramp. step 6. program the run frequency the run mode begins when external resistor r ph is charged to 5.1v. at this time, the run frequency is determined by the parallel combination of rt and r run along with r dt and c t . the run frequency can be programmed above or below the ignition frequency. f run is determined by the following equation: ph ph c e t ? = 6 0 . 4 ? ? ? ? ? ? ? ? + ? + ? ? = td c r r r r f t run t run t run 2 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = td f c r td f c r run t t run t run 2 1 1 1 2 1 1 ? ? = + ? + = 6 55 6 55 e v or e v r cs cs oc
ir2167(s) & pbf 30 www.irf.com component selection tips supply bypassing and pc board layout rules component selection and placement on the pc board is ex- tremely important when using power control ics. v cc should be bypassed to com as close to the ic terminals as pos- sible with a low esr/esl capacitor, as shown in figure 28. figure 28: supply bypassing pcb layout example a rule of thumb for the value of this bypass capacitor is to keep its minimum value at least 2500 times the value of the total input capacitance (ciss) of the power transistors being driven. this decoupling capacitor can be split between a higher valued electrolytic type and a lower valued ceramic type connected in parallel, although a good quality electro- lytic (e.g., 10 f) placed immediately adjacent to the vcc and com terminals will work well. in a typical application circuit, the supply voltage to the ic is normally derived by means of a high value startup resistor (1/4w) from the rectified line voltage, in combination with a charge pump from the output of the half-bridge. with this type of supply arrangement, the internal 15.6v zener clamp diode from vcc to com will determine the steady state ic supply voltage. c vcc (surface mount) d boot (surface mount) c boot (surface mount) c vcc (through hole) pin 1 ir2167 connecting the ic ground (com) to the power ground both the low power control circuitry and low side gate driver output stage grounds return to this lead within the ic. the com lead should be connected to the bottom terminal of the current sense resistor in the source of the low side power mosfet using an individual pc board trace, as shown in figure 29. in addition, the ground return path of the timing components and v cc decoupling capacitor should be con- nected directly to the ic com lead, and not via separate traces or jumpers to other ground traces on the board. figure 29: com lead connection pcb layout example these connection techniques prevent high current ground loops from interfering with sensitive timing component op- eration, and allows the entire control circuit to reject com- mon-mode noise due to output switching. c vcc (surface mount) c vcc (through hole) ir2167 pin 1 timing component s v bus return r cs (through hole)
ir2167(s) & pbf www.irf.com 31 caseoutline 20-lead soic (wide body) (ms-013ac) 01-3080 00 IR2167S
ir2167(s) & pbf 32 www.irf.com caseoutline 20 lead pdip (ms-001ad) 01-3079 00 ir2167 -
ir2167(s) & pbf www.irf.com 33 ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 data and specifications subject to change without notice. 1/29/2006 leadfree part marking information order information basic part (non-lead free) 20-lead soic ir2167 order IR2167S 20-lead pdip ir2167 order ir2167 leadfree part 20-lead soic ir2167 order IR2167Spbf 20-lead pdip ir2167 order ir2167pbf lead free released non-lead free released part number date code irxxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code

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